
`include "common_header.verilog"

//  *************************************************************************
//   File : top_xgxs.v 
//  *************************************************************************
//   This program is controlled by a written license agreement.
//   Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2005 Morethanip GmbH
//  info@morethanip.com
//  *************************************************************************
//  Version: $Id: top_xgxs.v,v 1.6 2008/01/16 21:01:24 mr Exp $ 
//  Author : Muhammad Anisur Rahman
//  *************************************************************************
//   Description:
// 
//   10 Gigabit Ethernet XGXS PCS Top-Level
// 
//  *************************************************************************

module top_xgxs (

   reset_sd0_rx_clk,
   reset_sd1_rx_clk,
   reset_sd2_rx_clk,
   reset_sd3_rx_clk,
   reset_xgmii_txclk,
   reset_xgmii_rxclk,
   xgmii_txclk,
`ifdef USE_CLK_ENA
   xgmii_txclk_ena,
`endif
   xgmii_txd,
   xgmii_txc,
   xgmii_rxclk,
`ifdef ENA_RX_RATE_MATCHING   
`ifdef USE_CLK_ENA
   xgmii_rxclk_ena,
`endif 
   jumbo_en,
`endif
   xgmii_rxd,
   xgmii_rxc,
   sd0_tx,
   sd1_tx,
   sd2_tx,
   sd3_tx,
   sd0_rx,
   sd0_rx_clk,
`ifdef USE_CLK_ENA
   sd0_rx_clk_ena,
`endif
   sd1_rx,
   sd1_rx_clk,
`ifdef USE_CLK_ENA
   sd1_rx_clk_ena,
`endif
   sd2_rx,
   sd2_rx_clk,
`ifdef USE_CLK_ENA
   sd2_rx_clk_ena,
`endif
   sd3_rx,
   sd3_rx_clk,
`ifdef USE_CLK_ENA
   sd3_rx_clk_ena,
`endif
   sd_signal0,
   sd_signal1,
   sd_signal2,
   sd_signal3,
  `ifdef MTIPXGXS_BUFRESET
   buf_reset,
  `endif   
   align_done,
   disp_err,
   char_err,
   cg_align,
   sync,
   pat,
   match_fault);  

`include "mtip_xgxs_package.verilog"

input   reset_sd0_rx_clk;       //  Asynchronous Reset - sd0_rx_clk Domain
input   reset_sd1_rx_clk;       //  Asynchronous Reset - sd1_rx_clk Domain
input   reset_sd2_rx_clk;       //  Asynchronous Reset - sd2_rx_clk Domain
input   reset_sd3_rx_clk;       //  Asynchronous Reset - sd3_rx_clk Domain
input   reset_xgmii_txclk;      //  Asynchronous Reset - xgmii_txclk Domain       
input   reset_xgmii_rxclk;      //  Asynchronous Reset - xgmii_rxclk Domain       
input   xgmii_txclk;            //  156.25MHz Transmit Clock
input   [63:0] xgmii_txd;       //  Transmit Data
input   [7:0] xgmii_txc;        //  Transmit Control
output  [63:0] xgmii_rxd;       //  Receive Data
output  [7:0] xgmii_rxc;        //  Receive Control        
output  [19:0] sd0_tx;          //  SERDES Lane 0
output  [19:0] sd1_tx;          //  SERDES Lane 1
output  [19:0] sd2_tx;          //  SERDES Lane 2
output  [19:0] sd3_tx;          //  SERDES Lane 3
input   [19:0] sd0_rx;          //  SERDES Lane 0
input   sd0_rx_clk;             //  SERDES Lane 0 Clock
input   [19:0] sd1_rx;          //  SERDES Lane 1
input   sd1_rx_clk;             //  SERDES Lane 1 Clock
input   [19:0] sd2_rx;          //  SERDES Lane 2
input   sd2_rx_clk;             //  SERDES Lane 2 Clock
input   [19:0] sd3_rx;          //  SERDES Lane 3
input   sd3_rx_clk;             //  SERDES Lane 3 Clock
input   sd_signal0;             //  SERDES Lane 0 Status        
input   sd_signal1;             //  SERDES Lane 1 Status        
input   sd_signal2;             //  SERDES Lane 2 Status        
input   sd_signal3;             //  SERDES Lane 3 Status
`ifdef MTIPXGXS_BUFRESET
   output [3:0] buf_reset;      //  Rset buffers when deskew error occured
`endif
output  align_done;             //  Lane Alignment Done
output  [3:0] disp_err;         //  Disparity Error Indication
output  [3:0] char_err;         //  Character Error Indication
output  [3:0] sync;             //  Channel Synchronization Indication
output  [3:0] pat;              //  Comma Detected Indication
output  [3:0] cg_align;         //  Code Group Alignment Indication
output  match_fault;            //  Rate Matching Error Indication

`ifdef USE_CLK_ENA
   input xgmii_txclk_ena;       // Enable xgmii_txclk
   input sd0_rx_clk_ena;        // Enable sd0_rx_clk
   input sd1_rx_clk_ena;        // Enable sd1_rx_clk
   input sd2_rx_clk_ena;        // Enable sd2_rx_clk
   input sd3_rx_clk_ena;        // Enable sd3_rx_clk
`endif 


`ifdef ENA_RX_RATE_MATCHING
  `ifdef USE_CLK_ENA
   input   xgmii_rxclk_ena;
  `endif   
 input   jumbo_en;               //  increase thresholds(=latency) to support jumbo frames
`endif 

wire    [63:0] xgmii_rxd; 
wire    [7:0] xgmii_rxc; 
wire    [19:0] sd0_tx; 
wire    [19:0] sd1_tx; 
wire    [19:0] sd2_tx; 
wire    [19:0] sd3_tx; 
`ifdef MTIPXGXS_BUFRESET
wire    [3:0] buf_reset;      //  Reset buffers when deskew error occured
`endif
wire    align_done; 
wire    [3:0] disp_err;
wire    [3:0] char_err;  
wire    [3:0] sync; 
wire    [3:0] pat; 
wire    [3:0] cg_align;
wire    match_fault;
wire    xgmii_rxclk_int;

`ifdef ENA_RX_RATE_MATCHING

   input   xgmii_rxclk;         //  156.25MHz Receive Clock    
   
   assign xgmii_rxclk_int = xgmii_rxclk ;

`else

   output  xgmii_rxclk;         //  156.25MHz Receive Clock

   wire    xgmii_rxclk;
   
   assign xgmii_rxclk_int = sd0_rx_clk ;
   assign xgmii_rxclk     = sd0_rx_clk ;
   
`endif

top_xgxs_tx U_TX (

          .reset_xgmii_txclk(reset_xgmii_txclk),
          .xgmii_txclk(xgmii_txclk),
          `ifdef USE_CLK_ENA
          .xgmii_txclk_ena(xgmii_txclk_ena),
          `endif
          .xgmii_txd(xgmii_txd),
          .xgmii_txc(xgmii_txc),
          .sd0_tx(sd0_tx),
          .sd1_tx(sd1_tx),
          .sd2_tx(sd2_tx),
          .sd3_tx(sd3_tx));

top_xgxs_rx U_RX (

          .reset_sd0_rx_clk(reset_sd0_rx_clk),
          .reset_sd1_rx_clk(reset_sd1_rx_clk),
          .reset_sd2_rx_clk(reset_sd2_rx_clk),
          .reset_sd3_rx_clk(reset_sd3_rx_clk),
          .reset_xgmii_rxclk(reset_xgmii_rxclk),
          .xgmii_rxclk(xgmii_rxclk_int),
          `ifdef ENA_RX_RATE_MATCHING
          `ifdef USE_CLK_ENA
          .xgmii_rxclk_ena(xgmii_rxclk_ena),
          `endif
          .jumbo_en(jumbo_en),
          `endif
          .xgmii_rxd(xgmii_rxd),
          .xgmii_rxc(xgmii_rxc),
          .sd0_rx(sd0_rx),
          .sd0_rx_clk(sd0_rx_clk),
          `ifdef USE_CLK_ENA
          .sd0_rx_clk_ena(sd0_rx_clk_ena),
          `endif
          .sd1_rx(sd1_rx),
          .sd1_rx_clk(sd1_rx_clk),
          `ifdef USE_CLK_ENA
          .sd1_rx_clk_ena(sd1_rx_clk_ena),
          `endif
          .sd2_rx(sd2_rx),
          .sd2_rx_clk(sd2_rx_clk),
          `ifdef USE_CLK_ENA
          .sd2_rx_clk_ena(sd2_rx_clk_ena),
          `endif
          .sd3_rx(sd3_rx),
          .sd3_rx_clk(sd3_rx_clk),
          `ifdef USE_CLK_ENA
          .sd3_rx_clk_ena(sd3_rx_clk_ena),
          `endif
          .sd_signal0(sd_signal0),
          .sd_signal1(sd_signal1),
          .sd_signal2(sd_signal2),
          .sd_signal3(sd_signal3),
          `ifdef MTIPXGXS_BUFRESET
          .buf_reset(buf_reset),
          `endif
          .align_done(align_done),
          .disp_err(disp_err),
          .char_err(char_err),
          .sync(sync),
          .pat(pat),
          .cg_align(cg_align),
          .match_fault(match_fault));

endmodule // module top_xgxs
